CSD – Chapter 1: Combinational Circuits

October 23

Three concepts left in Chapter 1 that will be covered in this class:

1) Implementing logic functions using the method of decoders.

2) Implementing logic functions using the method of multiplexers.

3) Gate-level simulation to determine how fast is the synthesised circuit (propagation time/ maximum speed of processing).

In this picture you can see that the Adder_5bit propagation delay in a given transition is 9.1 ns, thus the maximum speed of procession is 109.9 MHz

October 18

Today’s class on integer arithmetic is very important. The two’s complement convention. We have discussed in detail the specifications and the plan to solve the proposed P4 as the P_Ch1. Stuff covered:

  • Binary numbers, symbols, range, addition.
  • Conversion from binary to decimal, decimal to binary, hexadecimal numbers.
  • How to use the simple calculator in programming mode to works with bin/hex/oct/dec numbers.
  • The general architecture of an arithmetic and logic unit (ALU) and an example chip: 74LS181. The idea of performing in parallel all the operations and then selecting only one result.
  • How to represent positive/negative numbers (integers): two’s complement (2C) convention and range of values for a given number of N bits.
  • Operations with integers, overflow flag (OV): which is the algorithm to detect an overflow situation?
  • Play with the 8-bit adder/subtractor available in Proteus.
  • Play with a similar arithmetic circuit: the 7-bit signed multiplier.
  • Subtraction as a specific block build using individual Subtractor_1bit (see problem 1.4.3 in the CSD collection)
  • Addition: R = A + B. Subtraction: R = A – B = A + (-B) = A + 2C(B)
  • The idea of a XOR gate of 2 inputs as a programmable (CNTL) inverter/buffer to be used as a 2C generator module.
  • The improved plan for a 10-bit 2C adder/subtractor. Use it in your P4.

NOTE. There is no more classes on P4/P_Ch1. It is a self-directed learning material for you to be solved in cooperative groups. When finished, follow the instructions to upload it at the Atenea platform task (one project per group) before the due date (October 31). Ask questions if necessary.

October 17

Today we’ve solved and tested an Adder_5bit (P3_4) for practising on hierarchical designs using components and signals.

October 16

P3: Let’s explain the main ideas on VHDL hierarchical design based on COMPONENTS and SIGNALS at the same time that we learn arithmetic circuits. Basically, study, run and test Adder_1bit (P3_1), Adder_4bit (P3_2) and MUX_8 (Plan C2) (P3_3) tutorials.

On the other hand, learn how to add binary numbers using gates (Adder_1bit, Adder_4bit). Note how the 4-bit adder has two different plans: 1) ripple carry, 2) carry look ahead.

  • This is the template for the P_Ch1. Upload it at the Atenea task before the due date.

October 11

The list of projects being studied in this P2.

1h – Presentation of different (specifications: idea, symbol, truth table, timing diagram, commercial chips, etc.) combinational logic blocks: decoders, encoders, multiplexers, demultiplexers, hex-7seg decoders, etc. The main idea here is that any block can be designed using different plans like it is shown in the MUX_8 example.

1h:  Plan B of the MUX_8 design (P2_5). How to translate to VHDL the truth table or the algorithm of a circuit? Using schematics  and flow charts.

October 10

Let’s design the MUX_8 chip. For example the MUX_8 using a structural approach (P2_4). These below are some of the ideas discussed in class:

October 9

The HEX_7SEG_Decoder tutorial on running the ISE (synthesis) and ISim (simulation) tools:

Project P2_2: Design the HEX_7_SEG circuit using a structural approach (equations).

Project P2_3: Design the HEX_7_SEG circuit using a behavioural approach (truth table).

October 4

NOTE: Complete the projects that we start in class. You must do it in order to learn correctly the specific content of the course. By now we have discussed up to 8 projects and tutorials for P1. (which is at least 8 x 4 = 32 individual dual face sheets of paper)

Be neat, fair and stick to the rules: every project in different sheets and organised as you know: 1) specifications, 2) planning; 3) development; 4) test and verification. And remember that each one of these four project sections goes in a different sheet of paper. Ask questions if necessary.

Today we’ve completed the example tutorial on running the VHDL tools :

  1. Specifications: Find the truth table of the Circuit_W using VHDL synthesis and simulation tools (This is the project in P2_1).
  2. The plan is:


  1. Write the VHDL source file from a similar file in digsys.upc.es (P2). VHDL source file example Circuit_W .vhd.
  2. Start a new project for a XILINX target FPGA chip like the : Spartan-3E XC3S500E-FG320
  3. Run the synthesis process and examine the RTL view and the technology view. Annotate and commend the differences.
  4. Prepare a VHDL test bench file from the template and adding input stimulus.  VHDL test bench example Circuit_W_tb.vhd.
  5. Run the simulation process and extract the truth table from the inspection of the logic analyser display.

3.- Development

4. Test and verification


October 3  COMUNICAT:

Amb motiu dels episodis de violència, injustificada i injustificable exercida a Catalunya l’1 d’octubre per la guàrdia civil i la policia nacional, manifestem el nostre rebuig, la nostra indignació i la nostra condemna més enèrgica.

A la UPC creiem que l’ús de la força contra els ciutadans i ciutadanes és intolerable en democràcia i que la violència –per definició–, no pot ser mai proporcionada.

Més enllà de les diverses posicions polítiques de totes les persones que integren la comunitat de la UPC, coincidim a reiterar que l’única via possible en qualsevol conflicte és el diàleg i no ens cansarem de reivindicar-lo com a única arma legítima en democràcia.

Per tot això, la UPC se suma a l’aturada de país prevista per a demà, dia 3 d’octubre.

Se suspenen les activitats i els edificis romandran tancats

Atès que la UPC s’adhereix a l’aturada de país del 3 d’octubre, se suspenen les activitats, els edificis romandran tancats i no hi haurà serveis mínims.


October 2

let’s start the project P2, on simple combinational circuit design discussing how a VHDL file looks like: entity and architecture. Let’s describe the Circuit_W using its structural equation. So that by October 4, we can use this file (Circuit_W) adapted from here as the source file for running the VHDL synthesis and simulation process to obtain its truth table.

It is possible to describe entities using two approaches for the architecture:

1) structural (circuit/equation)

2) high level behavioural description (algorithm/truth table).


September 27 (today is Monday at the EETAC)

Today we’ve discussed about the many different projects that can be solve applying in some way or another the basic concepts such as maxterms, truth table, etc.

Solve any of these Circuit C, Circuit_K, Circuit A or Circuit B

1. Analysis for determining their truth table;

2. Design of different type of circuits from the initial truth table:

  • Project: Design a XOR of 3 inputs using only NAND of 2 inputs. Remember that the problem solution must be organised as follows:
    • Specifications and theory.
    • Planning.
    • Development of the plan.
    • Test/verify/check and discuss the solution.


September 26

Today we’ve solved a tutorial on the use of Minilog.exe application to minimise logic functions.

  • Project 1: From the truth table of the function W 0 f(D1, D0, A, B) obtain a circuit (Circuit 3) that is derived using minilog and SoP.
  • Project 2: Transform the previous Circuit_3 into a new one where all the gates are NOR.

September 20

Firstly, we’ve discussed about the 3rd and 4th methods for analysing a given circuit based on solving the circuit manually, this is using concepts like SoP or Pos, maxterms and minterms and the Boolean tricks for transforming logic terms.

–  Apply the same tutorials for solving Circuit_C and any other circuit you like.

Secondly, we’ve seen the design concept, where the initial data (specifications is the truth table), and so, you like to obtain (synthesise) different type of circuits: canonical, simplified, using only-NAND, using only-NOR, etc.

So, the next Monday class will be for minimising circuits using espresso algorithms (minilog or Logic Friday).


September 19

  • This is today’s Circuit_W that we have adapted in Proteus from this original one in the Proteus tutorial:

  • This is today’s equation.txt for run WorframAlpha calculations

September 18

This is the idea for organizing how to study and report each problem/project (now using sheets of paper, later using a word processor):

  1. Specifications
  2. Planning.
    1. Detailed plan 1
    2. Detailed plan 2
    3. …..
  3. Development
    1. Development of the Plan 1 to find the solution
    2. Development of the plan 2 …
    3. …..
  4. Test/verify/check the solutions

And this is the general plan for the P1, which has this simple specifications: Let’s obtain the truth table of the Circuit_C

  • The other day I forgot to tell you that I’ll only answer your emails if you follow these rules.

September 13

This is the course starting point: P1 on circuit using logic gates. We’ll try to solve a circuit every week and a synthesis or design project every four weeks when the chapter ends.

This is my timetable in case you like to ask questions or have some tutorial time.

Let’s analyse the Circuit_1C and the Circuit 1D in different ways in order to get in touch with the Boole’s Algebra. Analyse (and this is an example concept map) means to deduce its truth table, thus the way it works.

  • Check your Citrix credentials once the Receiver installed in your PC and through this web:

September 12

Question: What if I cannot attend class until next week?

Answer: Hi, I think that it is not a problem if you cannot attend classes until the next week. We’ll discuss the P1 which is online, so you can study it by yourself. 

Try to find two mates of the same class-subgroup for organising a cooperative group for solving lab projects and exercises.



RPi – Capítol 3: Circuits electrònics

7 de juliol

Avui triarem projecte (especificacions, planificació, desenvolupament i test) per grups de treball i ja personalitzarem les discussions als requeriments de cada grup. El treball final es pot presentar per email fins al dia 14 de juliol. Podeu usar els materials fins aquest dia i discutir els vostres projectes amb l’instructor.

6 de juliol

El que em cal destacar és l’ús d’interrupcions per poder detectar canvis de nivell lògic en polsadors.

P12: Per poder dissenyar circuits digitals ja de certa entitat necessitem basar-nos en el concepte de FSM (màquina d’estats finits) o sistema seqüencial i de com s’estructura el programari en Python per resoldre les tasques que ha de dur a terme el diagram d’estat de la FSM. Hem discutit l’exemple del semàfor, que a partir d’una planificació inicial, es pot anar complicant seguint diverses fases.

P13: I a partir d’aquests projectes ja podrem introduir-nos en sensors i interfícies més complexes o d’alt nivell (SPI, I2C, etc.). Hem comentat el tema del bus I2C en què amb un parell de cables, serial data (SDA) i serial clock (SCL) es poden connectar multitud de sensors cadascun d’ells amb una adreça diferent. I la possibilitat d’adaptat els nivells de voltatge (de 5 V a 3,3 V) quan el sensor s’alimenta a aquesta tensió de 5 V no suportada per la Raspberry Pi.

5 de juliol

P9: Hem introduït el llenguatge Python perquè és el que més s’ha utilitzat en el món de la Raspberry Pi fins ara. I per tant hi ha molt de material, llibres i exemples per poder començar còmodament.

P10: Però si voleu per ara, o potser per més endavant, teniu disponibles biblioteques de funcions d’interfície per una quants llenguatges més.

P11: Aquí comencen pròpiament els exemples amb el connector GPIO. Hem fet un parell de circuits amb LED i amb polsadors.

  • Insistim en l’anàlisi dels circuits i dels programes de mostra amb l’objectiu de dibuixar el seu diagrama de flux.

RPi – Capítol 2: Aplicacions estàndard d’escriptori i programació

Dimecres 5 de juliol

P7:  Quines aplicacions educatives en general us interessen?

P8:  Si voleu convertir la Raspberry Pi en un servidor web i/o de WordPress.

Fixeu-vos que si ho voleu, ja podeu concentrar-vos o intensificar en el desplegament d’alguna aplicació contreta: simulació de circuits, eines ofimàtiques, construcció d’un mediacenter, etc.


Dimarts 4 de juliol

P5:  Què tenim a l’escriptori Raspbian?

P6Mediacenter KODI. Recomanable d’instal·lar també en un PC per provar-lo i habituar-se al seu entorn.


RPi – Capítol 1: El micro PC Raspberry Pi

Curs d’introducció a la Raspberry Pi.

4 de juliol de 2017

P3: Simplement presentar alguns comandaments senzills en mode text del sistema operatiu. També l’entorn gràfic, que s’assembla al Windows de Microsoft. Realment el Linux, amb les seves variants (Ubuntu, Debian, Linkat,(proposat pel Departament d’Ensenyament) etc., dona una alternativa molt vàlida en codi obert al Windows 10.

P4:Control i ús remot de la Raspberry Pi. Haurem de permetre que la R-Pi 3 tingui habilitades les interfícies VNC i SSH.

PuTTY: Connexió entre ordinadors SSH en mode text. La versió de la Raspberry ja està instal·lada per defecte.

VNC: La versió RealVNC ja està instal·lada gratuïtament a la Raspberry Pi. Modes viewer i server.


3 de juliol de 2017

Comencem pel primer treball P1 del curs. Instal·lació del kit i conceptes bàsics de la Raspberry Pi.

P1: Instal·lació bàsica. Configuració del teclat.

  • En primer lloc canviarem el password original “raspberry” de l’usuari pi.
  • Com es pot escollir el sistema operatiu? Perquè la targeta que subministra el kit per defecte ja arrenca per defecte en Raspbian. Entre quants sistemes operatius podem triar? Imatge NOOBS.
  • Com es descarrega la imatge des de la web oficial? Com es fa una còpia de seguretat de la memòria SD per si hi ha problemes, se’ns desconfigura i hem de tornar enrere?

P2: Data i hora. Ens hem trobat que els tutorials funcionaven en unes Raspberry Pi i no pas en altres. On està el problema?

Connexió manual (sense DHCP) a una una adreça fixa d’Ethernet, aprofitant que els llocs de treball del laboratori tenen cable i connexió a un switch. Així no cal entrar cada dia com usuari convidat.

  • Revisar els fitxers de sistema on es guarda la configuració de la WI-Fi i de cable Eth0.


CSD – P12: Real time using TMR2

Thursday 25

  • This is a new paper precisely on the key importance of the CLK device: Liming Xiu, “Clock Technology: The Next Frontier“, IEEE Circuits and Systems Magazine, 2017.  Perhaps you manage to download the full PDF from a UPC computer like Citrix using this eBIB tool. If not, ask me by email, and I’ll send it to you. It’s interesting to see how deep goes the research subject thinking only on CLK issues.
    Let’s introduce the way to program an application using the TMR0, so that later you can program a similar embedded timer peripheral in the PIC18F4520 microcontroller: the timer 2 (TMR2).

The idea of real time (seconds, minutes, etc.) is developed around counting pulses from a stable and accurate crystal oscillator.

This is the class discussion (1) and (2), where some ideas were given around the way to study the tutorials and how to program the TMR0 to develop applications like counting people coming into the library (events counting) or counting real time (timer from a precision CLK source).

Use the tutorial in P11 (fixed 18.5 s timer) to see how your sketches can be translated to C code.  It’s convenient to print in colour this code and analyse it. And the same with the timer structure, print the 3 pages of the PIC18F4520 datasheet chapter on TMR0.


CSD – P11: Adding an LCD display

May 23

In this P11, we’ll enhance the basic FSM, the Johnson counter developed in P10, with an LCD display to be able to write  ASCII messages, for instance indicating the the internal state of the machine, like: “Click the Start button”, or “State #1”, or “Click to Stop the sequencing”, etc.

Thus, you can attach an LCD to P10 when you have finished at least one of the P10 design phases.

Adding the LCD means learning about the peripheral itself, like the standard LM032L, and finding a library of C functions compatible with the C compiler (XC8) for the high-level handshake with the device . This is an introduction to the Microchip Peripheral Library (PLIBS). And, it may be even automatised using a tool like the MPLAB® Code Configurator (MCC).

CSD – P10: FSM using microcontrollers. A 6-bit Johnson counter

May 27

Let’s readjust the project phases and grading after some feedback from you. It looks like that solving the Phase #1 takes more time than initially estimated:

Phase #1 –> 8 p; phase #2 –> 2p;  phase #3 –> optional

Phase #3 can be incorporated later in P11 along with the LCD display.

May 24

This is a checklist for P10 proposal, as you has asked me in class.

Thursday 18

  • Today we’ve had an important tutorial class on the basics of FSM applied to programming microcontrollers studying the BCD_Counter. You can continue the tutorials by your own because the required materials are online. The idea is to adapt what you’ve learned on the design of the 6-bit Johnson counter.

Wednesday 17

  • Compiler data types and variables. Most of our variables in these introductory programmes will be “char”, which occupy a byte of RAM memory.

Tuesday 16

This is the project discussion (1), (2) on the Johnson counter to be implemented in this P10. How to solve a basic sequential circuit in C and using a microcontroller?

To comprehend the main ideas, and to plan your project, follow the tutorial examples BCD_counter, and the 74HCT4017 chip.




CSD – P9: Introducing microcontrollers. Basic I/O. 1-digit BCD adder

May 24

This is the checklist discussed containing most of the concepts.

May 20


I am doing P9, but I have some doubts about how to write the code. I download the PIC18F4520 from development of digsys web, but I don't know how to write the code. I am following the steps of init_system, read_inputs, truth_table and write_outputs, but I don't know exactly what I have to write. 


Well, this is a general question ... better to find some time in office on Monday before 11h or after 16h, so that we can program something. 

Here you are some insight on how to start. The code I gave you that was run in class has only some connections and only the variable Value_Cin implemented in read_inputs(), so:

1. Start a project using both hardware and C source files. 
2. Compile and run to watch the variable Value_Cin.
3. Add some code to read_inputs(), for example to read the A(3..0) and convert it to Value_A. Firstly add the wires in the hardware circuit, and draw in paper the bitwise operations required. This is example of how you can organise the reading of a variable. 
4. Compile and run to watch the variable Value_A.
5. Etc... read B(3..0) the same way. 
6. Check if error in the A or B range.
7. Implement the truth table. If no error, (1) start adding in binary, and later (2) implement the BCD correction algorithm. 
8. Write the outputs. These (1) - (2)  are examples on how to write a given variable using bitwise C instructions. 
9. Run and check it all. 
10. Print your C code and a couple of images on how the circuit works. 


May 11

Comments on planning the P9. After having run the tutorial examples, the general idea is: 1) understand the problem, 2) plan a small step like reading an input variable, 3) develop the project so that you can 4) test it. Once it works fine, add some new instructions, for example for reading another variable, and repeat it all.

Meanwhile you solve these examples, it is recommended reading about microcontroller architecture and programming in any book or web page. Browse the vendor web sites too, like microchip.com.

Browse previous blog entries on P9 (1) to see similar class notes and ideas.

May 9

We’ve discussed the basics of microcontrollers (theory and tools), and we’ve explained how the tutorial example Dual_MUX4 is organised and how you can run the IDE to obtain the output COF file to enable debugging.

This is a tutorial, thus the C code is complete. However, in the BCD_Adder, better to go step by step, for instance reading only Cin pin and watching the variable Value_Cin to see if it’s been captured correctly compiling and debugging repeatedly.

May 4

This is the architecture of the PIC18F4520 to be used in this Chapter 3 on microcontrollers.

CSD – P8: Timer with keypad and CLK generator

May 15

Some ideas discussed in office time about the Control_FSM.

May 5

Due date for P8 : May 17. This time, like in P7, you must show skills for organising the project check/grading list. As a general rule, Description/planning of the main project Timer_keypad is 4p, and the design of the chip is 6p.

Only one report per cooperative group.

May 4

The class discussion on the CLK generator and its proposed internal architecture. This is counter in Proteus (unzip it and run) to demonstrate the basic principles.

May 3

This is the assignment of components- chips for each cooperative group. The idea, as you see is to draw the RTL of the timer_keypad project, and then that every group solves a different component.

May 2

This project is too large to be solve by a single cooperative group in the given time of 10 hours, thus several teams will cooperate to solve it building the different components and the top schematic. The planning gives indications on the steps to follow to complete the design:

  1. CLK_generator. Chip6.
  2. BCD_BIN_converter_2dig. Chip4.
  3. matrix_encoder_16key_registered. Chip1. The modified P6.
  4. data_reg_4bit. Chips2 and 3.
  5. Programmable_timer. Chip 5 (P7).
  6. Control_FSM. Chip 7.
  7. Top schematic Timer_keypad, synthesis and simulation.


CSD – P7: Programmable timer

May 5

Due date for P7 : May 17. This time, you must show skills for organising the project check/grading list. As a general rule, Description/planning of the main project Programmable_timer is 4p, and the project for designing the chip is 6p.

Only one report per cooperative group.

May 3

This is the assignment of components to each cooperative group. The idea, as you see, is that each team is responsible of the design of a different component in a way that the collaboration of everybody is required to succeed in finishing the P7. Specifically, all the components are in place and finished, except the Chip1 (Timer_FSM) in the Programmable_timer schematic, and the Chip8 (counter_8bit) in the Timer_datapath schematic.

Be aware that our final objective, even if you are in charge of only one component, is to comprehend the complete P7 project.

April 28

Next week we’ll decide how to organise the design in cooperative groups.

April 25

Let it be P7 a programmable timer conceived as a dedicated processor where an 8-bit synchronous down counter is pre-set (parallel load) to different values, so that enabling different timing periods. With the information you’ve go in the web page, when down counting in binary, we can count 255 pulses.

But because we like to connect this device to the P6 keypad we’ll enter 2 BCD digits, thus counting  only from 00 to 99 as maximum, thus in P8 we’ll add an external component BCD to binary translator to connect the P6 keypad to the programmable timer.