CSD – Chapter 3: Microcontrollers

December 5

  • New project using Atmel Studio 6.2. Let us see how to start a new project, compile and debug code using simultaneously both the Atmel Studio and the Proteus: learning step-mode of operation, code breakpoints, execution time measurement, and debug using the watch window.  For instance, capture/sample/read the Ch2(1..0)  input bits –> pict_1 (hardware connexions); pict_2 (Port C bit 4 as input, Port B bit 7 as input); pict_3 (code) ; pict_4 (results using the watch window).

  • Let’s adapt now the tutorial to the BCD_Adder. Firstly the hardware, and then the software

December 4

P9: This below is the whiteboard discussion of the tutorial Dual_Mux4 hardware and software organisation. Tomorrow we’ll learn about how to read and write data from and to microcontroller port pins.

November 29

P9: Let’s start with microcontroller chips. The idea is to implement applications like the ones seen in previous charters but using a microcontroller and the C language. This course we’ll use an Atmel ATmega8535 chip from Microchip, Atmel Studio 6.2 integrated development environment (IDE) and Proteus VSM as the simulation tool.There is a tutorial example that we’ll discuss in class: Dual_Mux4.

CSD – Chapter 2: Sequential systems

December 10

NOTE: Citrix virtual has not been working for two days now. It cracked or hanged on Saturday and it cannot be accessed. There is no maintenance service on weekends and it has to be repaired next Monday. So, we’ll delay de P_Ch2 due date by Thursday 14 at 13.00.

 

December 7 (more questions and answers by email)

We have a doubt and it is to check the number of registers of the clock generator.We only find this on the blog: “The name of the source file is JK_Flip_Flop.vhd. Run the EDA tool to synthesise the circuit and print and comment the RTL schematic. Check the number of registers (DFF) used in the target chip. In this simple example, the answer has to be a single DFF register.

Yes, if you are synthesising a single JK-FF which is a 1-bit cell of memory, only a D-FF is required (it is a state machine of 2 states).

Now imagine that our CLK_generator has a single output like CLK_20Hz_SQ and the OSC_CLK_in is 50 MHz. So, it has to divide by 2.500.000 and so, the number of bits required to reach such a large counter of 2.5M states is: 22 (with 22 bit you can count in binary up to 4.194.304). In this case you need 22 D-FF.  The summary report of the synthesis EDA tool has to show you this information on the number of registers D-FF used. 

Yes but I can not find it here: ​Perhaps it is inside the synthesis report? I found it but I am not sure…

I see that “number of slice flip-flops” = 31.  Or instead: 7-bit counters 3*7  = 21; 5-bit counters 1 *5 = 5; and 5 registers == 21+5+5 = 31.   So, this is the number of D-FF that your design is using. You can check with your plan, whether this number is correct or not.  As you see, every slice in the Spartan 3E contains a pair of memory cells data flip-flop. Time to time is convenient to read a bit of the databook, the technology of the programmable chip, because by now you will be able to identify a lot of logic and arithmetic blocks.

December 6 (questions and answers by email)

Hi Francesc,  We have already finished the Timer_MMSS but we have a few questions:
1- Is it necessary to include the code to translate the BCD signals (DMT, DMU, DST, DSU) into 7-segment (BCD_7seg_decoder)?

No. This issue belong to the optional section 5: prototyping the design in a board like the NEXYS 2 from Digilent. You’ve invited to do it later, for instance by January after your exams. This is multiplexed display system (mds) in Proteus (video) from former 11/12Q2 term that was used there to implement a bicycle speedometer. This is the complete component MDS for adapting the NEXYS 2 which must be included in the top Timer_MMSS_NEXYS2 to drive the 7-segment displays with the MM and SS data.

2- Is it necessary to create the Button_synchroniser inside the Control Unit?

No. This issue is optional too. It allow me to explain you another concept: the synchronization of external signals to better work with a synchronous circuit and avoid uncertainty and improve reliability. But as said, it’s optional. It is the FSM that has the 3 states shown in the whiteboard.

3- We have created a test bench to test the Timer_MMSS but there is a problem, the simulation is so slow that it is impossible to see how the Timer works. We think that it is because of the CLK input is 50 MHz and the signal it has to count down is 1Hz (it takes a lot of time to generate the 1Hz signal). Something similar happened in the ClockGenerator test bench too.

Yes, it’s predictably too slow due the many frequency divisions from the initial CLK of 50 MHz. A way to speed up the circuit response while simulation is “fake” the frequency dividers, for instance the freq_div_125. Leave it as it is, but simply replacing the:
CONSTANT Max_Count    : STD_LOGIC_VECTOR(6 DOWNTO 0)     := “1111100”; — 124

by:
CONSTANT Max_Count    : STD_LOGIC_VECTOR(6 DOWNTO 0)     := “0001001”; — 9 — > the same number of wires, but more faster (it is a divider by only 10 now), so it’ll speed up the simulation (the 1 s period is now 12.8 ms).  Here you are a helpful test-bench with convenient times for clicking the buttons and a picture. (Later on, when doing it for real in a board if this is the case, replace the constant Max_Count to its original value 124, to obtain the “real-time” of 1 second).

Thank you very much for your interest and engagement in the subject and the quality of your questions that will help everybody else to succeed in solving this project.

December 2 (questions and answers by email)

  • HINT: Here you are the top architecture of the dedicated processor Timer_MMSS adapted from this schematic discussed in class. The components’ architectures are empty now, but the EDA tool synthesise it to recognise an RTL view picture like the one below (click to expand):

  • How to proceed with the design of the CLK_generator (all the section 1 in assessment list)?

1) Study the symbol and the plan. Comprehend why such frequency dividers and TFF are used and chained together.

2) Study the translation to VHDL of a counter/frequency divider block like Freq_div_100 available below by Nov 20 for the light_system_NESYS2 project (source files). Here you need to generate Freq_div_125, Freq_div_80, Freq_div_20, and a Freq_div_2 (hint: this is the component solved in 2 different versions: V1, V2, choose one of them). Adapt too the schematic CLK_generator.

3) Convert to VHDL your plan, synthesise it, inspect the RTL and test the CLK_generator behaviourally and at the gate-level in order to be able to measure the propagation time t_CO  and the maximum frequency of operation f_max.

  • How to proceed with the design of the Counter_MMSS and the datapath blocks (all the section 2 and the 3.1 in assessment list)?

Look at the symbol sketched in this picture,  which is the first item in the specifications of the datapath. As we discussed in class, better you, as a cooperative group, do not go away from the design path that we’ve discussed together and is reported in the blog:

1) Study how the (BCD 2-digit synchronous) counter_mod24 works, based on counter_mod16 universal binary counter. Take your time because your objective is to design a very similar block: the counter_mod60

2) Once understood, modify the counter_mod24 to adapt it to be the counter_mod60. Synthesise and test it using the same testbench stimulus signals that I gave you for the counter_mod24.

3) Use 2 blocks counter_mod60 to build the Counter_MMSS which is precisely the Chip1 in the datapath. Synthesise and test it using the same stimulus signals as before.

4) Finish the datapath block adding to the schematic the MUX_2 Chip2 and Chip3 and Chip4 (Chi3 and Chip4 can be replaced by simple AND gates. Print its RTL view.

  • How to proceed with the design of the Timer_MMSS (section 3 in assessment list)?

Only once the sections 1 and 2 are completed (the schematic of the CLK_generator and the datapath). Basically it is about writing the Control_unit FSM in a single file, and complete the top schematic composed of the Chip1 (datapath), Chip 2 (control_unit) and Chip 3 (CLK_generator)

1) Study the plan for the control_unit. State diagram, etc.

2) Adapt the file from Nov 20 on the light_system FSM.

3) Write the top schematic Timer_MMSS and synthesise it. Inspect the RTL and try to simulate it inventing a testbench for the push-buttons.

November 28

P_Ch2 due date: December 11.  This is the organisation and assessment checklist. Thus, working in your cooperative group, you can go step by step solving one section at a time until you complete the different circuits involved in the project. Ask questions when necessary.  

The internal architecture of the datapath and the FSM for the control unit:

And the FSM for the control unit. Additionally, you can even add another FSM component: the start button synchroniser, able to generate a single pulse when clicking: 

November 27

We’ve discussed the P_Ch2 specifications (MMSS_timer) and how to start planning it.

  • The programmable timer implemented as a dedicated processor composed of a datapath and a control unit.

  • On how to divide frequency by a number N (freq_div_N) and how to square signals:

  • And so, the idea for the conception of the CLK_Generator:

November 24

The same Thursday class at the same time, but with more materials to discuss:

  • The P. 2.3.6 is the building block universal Counter_mod16 discussed in class. This is the plan (1) and (2) conceived as a single file FSM, and this is its VHDL description and example test bench in case you like to run the EDA tools for synthesising and testing. This below is a timing diagram:

  • To learn better how to implement truncated counters, perhaps you like to try first the simpler project P. 2.3.7.

– This is a solution for the plan A: hierarchical design along with its translation to VHDL for you to develop the project and simulate it as shown below:

– This is a solution for the plan B: single file FSM design along with its translation to VHDL for you to develop the project and simulate it. You must obtain the same timing diagram above when zooming all. And below is the image of the CLK to output propagation time measurement obtained when running the gate-level simulation:

Try to finish the projects, ask questions and do not hesitate to use my office time.  We’ll schedule another class for solving problems by mid December.

November 23

A 1-hout class (13:00-14:00) for solving example problems from the CSD collection or previous exams.

This is the discussion on the P. 2.3.5 of the collection: an hour up/down counter (synchronous BCD counter module 24 with the option of two output codes, 00 – 24, and PM/AM) :

  • Understand the problem (specify it), and then infer a plan, like: a) convert a counter_mod16 into a counter_mod10, and b) use 2 counter_mod10 to implement the hour_counter. This is the full discussion (there was a bug corrected with the help of Guillem Delgado). This is the complete project development using the many components and below is a demonstration of waveforms:

Perhaps you can study the problem better if you consider for simplicity that firstly the hour_counter goes only UP.

The Counter_mod60  for the P_Ch2 can be solved in the same way.

November 22

  • P7: Data and shift registers. Units 2.7 and 2.10 have examples of these basic sequential building blocks.

  • This below is the P_Ch2 specification (MMSS_timer). Due date: December 11. It is a programmable timer like a commercial one: 2 buttons to setup the real time (MM:SS) at a 20Hz rate, another button to start (ST) the down-counting and  another one to stop (SP) the alarm. There is a LED to indicate that the count down has reached 00:00 and also a sound wave of about 1.5 kHz period.  The time-base is derived from a 50 MHz quartz crystal oscillator. The system can be implemented in the NEXYS 2 board. 

November 21

P7: Let’s design counters, data and shift registers.

Below there are some notes of theory on counters. Play with the counters modelled in Proteus and finish the design of the Counter_mod16: 1) Specifications; 2) Planning; 3) Development; and 4A) Test functional, 4B) Gate-level. Determine the maximum speed of the counter targeted for an Spartan 3E XC3S500E-320

General ideas on the universal counter (symbol, function table, state diagrams. Write down an example of timing diagram and infer a plan using a FSM.

Using these strategies you can build many counters: binary, BCD, One-hot, Gray, Johnson, etc.

You can expand the number of states chaining counters together in a given way:  BCD modulo 60 counter, binary 1024, etc.

Probably, the P_Ch2 will be de design of a real-time clock derived from the Digilent NEXYS 2 50 MHz oscillator. A programmable timer for instance.

November 20

Let’s finish the light_system FSM project:

3. Development. Let’s continue the light_system problem. Find a similar VHDL file and adapt it to the FSM.

4.- Test and demonstration. Run a functional and a gate-level simulation to check that the circuit works as expected.

These are the example files once adapted and this below is a typical capture that shows how does it work:

  • Additional demonstration:  This is the complete project light_system_top prototyped in a NEXYS 2 board populated with a Spartan 3E FPGA (follow too the tutorial on the LED flashing light, which is very similar). This is the class discussion on the 3rd and 4th design steps:

November 17

  • Class at the 128B for the group 3GT3 (or any other student who may like to solve problems). A repetition of the Thursday class.

The class discussion:

November 16

  • Class at 239V for the group 3GM1 (or any other student who may like to solve problems). We’ve solve the problem 2.2.3 of the CSD collection. Material that is also prepared as a tutorial in P5 learning materials: Asynchronous circuits.

November 15

  • Go and vote for the rector of the UPC
  • Infer the D-FF from an RS-FF.
  • P6: Using the D-FF as the memory cell in the state register of a FSM. Example of a FSM: Classroom ON/FF lighting system.

This is a list of the projects solved in P6.

1. Specifications:

2. Plan:

November 14

This is a list of the projects solved in P5.

Let’s continue with the internal design of the 1-bit memory cells:

  • RS latch

  • RS_flip_flop

November 13

P5. Let’s start the Chapter 2 with the 1-bit memory cell: RS latch (asynchronous), and JK, D, T, and RS flip-flops (synchronous). This is the new building block that is going to be used along with combinational circuits to implement finite state machines (FSM).

How to deduce an RS flip-flop from a RS latch? Use these notes as the starting ideas on sequential systems

CSD – Chapter 1: Combinational Circuits

November 6

October 25

 

  • More example everywhere in Digsys web older terms – tests and in this blog (search CSD IT1)

October 24

  • Gate-level simulation to determine how fast is the synthesised circuit (propagation time/ maximum speed of processing).

This is the problem (Combinational_circuit) that we’ve finished today in the lab using the method of multiplexers. Gate-level (post-route) measurement on the technology view circuit has given propagation delays of about 7 ns, meaning 142 millions of operations per second (Mops). Here the concept of an operation is the computation of a truth table vector.

  • On the other hand, in this picture you can see that the Adder_5bit propagation delay in a given transition is 9.1 ns, thus the maximum speed of processing is 109.9 MHz. Here processing is solving a 5-bit binary addition.

NOTE: Finish some projects from P1 to P4 and add the final gate-level simulation to them to measure how fast the circuit is for the target FPGA chip Spartan 3E XC3S500E-320 or any other programmable Xilinx chip.

October 23

Two concepts left in Chapter 1 that will be covered in this class:

1) Implementing logic functions using the method of decoders. Some circuits in VHDL to copy and adapt.

2) Implementing logic functions using the method of multiplexers.


October 18

Today’s class on integer arithmetic is very important. The two’s complement convention. We have discussed in detail the specifications and the plan to solve the proposed P4 as the P_Ch1. Stuff covered:

  • Binary numbers, symbols, range, addition.
  • Conversion from binary to decimal, decimal to binary, hexadecimal numbers.
  • How to use the simple calculator in programming mode to works with bin/hex/oct/dec numbers.
  • The general architecture of an arithmetic and logic unit (ALU) and an example chip: 74LS181. The idea of performing in parallel all the operations and then selecting only one result.
  • How to represent positive/negative numbers (integers): two’s complement (2C) convention and range of values for a given number of N bits.
  • Operations with integers, overflow flag (OV): which is the algorithm to detect an overflow situation?
  • Play with the 8-bit adder/subtractor available in Proteus.
  • Play with a similar arithmetic circuit: the 7-bit signed multiplier.
  • Subtraction as a specific block build using individual Subtractor_1bit (see problem 1.4.3 in the CSD collection)
  • Addition: R = A + B. Subtraction: R = A – B = A + (-B) = A + 2C(B)
  • The idea of a XOR gate of 2 inputs as a programmable (CNTL) inverter/buffer to be used as a 2C generator module.
  • The improved plan for a 10-bit 2C adder/subtractor. Use it in your P4.

NOTE. There is no more classes on P4/P_Ch1. It is a self-directed learning material for you to be solved in cooperative groups. When finished, follow the instructions to upload it at the Atenea platform task (one project per group) before the due date (October 31). Ask questions if necessary.

October 17

List of projects being studied in this P3.

Today we’ve solved and tested an Adder_5bit (P3_4) for practising on hierarchical designs using components and signals.

October 16

P3: Let’s explain the main ideas on VHDL hierarchical design based on COMPONENTS and SIGNALS at the same time that we learn arithmetic circuits. Basically, study, run and test Adder_1bit (P3_1), Adder_4bit (P3_2) and MUX_8 (Plan C2) (P3_3) tutorials.

On the other hand, learn how to add binary numbers using gates (Adder_1bit, Adder_4bit). Note how the 4-bit adder has two different plans: 1) ripple carry, 2) carry look ahead.

  • This is the template for the P_Ch1. Upload it at the Atenea task before the due date.

October 11

1h – Presentation of different (specifications: idea, symbol, truth table, timing diagram, commercial chips, etc.) combinational logic blocks: decoders, encoders, multiplexers, demultiplexers, hex-7seg decoders, etc. The main idea here is that any block can be designed using different plans like it is shown in the MUX_8 example.

1h:  Plan B of the MUX_8 design (P2_5). How to translate to VHDL the truth table or the algorithm of a circuit? Using schematics  and flow charts.

October 10

Let’s design the MUX_8 chip. For example the MUX_8 using a structural approach (P2_4). These below are some of the ideas discussed in class:

October 9

The HEX_7SEG_Decoder tutorial on running the ISE (synthesis) and ISim (simulation) tools:

Project P2_2: Design the HEX_7_SEG circuit using a structural approach (equations).

Project P2_3: Design the HEX_7_SEG circuit using a behavioural approach (truth table).


October 4

NOTE: Complete the projects that we start in class. You must do it in order to learn correctly the specific content of the course. By now we have discussed up to 8 projects and tutorials for P1. (which is at least 8 x 4 = 32 individual dual face sheets of paper)

Be neat, fair and stick to the rules: every project in different sheets and organised as you know: 1) specifications, 2) planning; 3) development; 4) test and verification. And remember that each one of these four project sections goes in a different sheet of paper. Ask questions if necessary.

Today we’ve completed the example tutorial on running the VHDL tools :

  1. Specifications: Find the truth table of the Circuit_W using VHDL synthesis and simulation tools (This is the project in P2_1).
  2. The plan is:

 

  1. Write the VHDL source file from a similar file in digsys.upc.es (P2). VHDL source file example Circuit_W .vhd.
  2. Start a new project for a XILINX target FPGA chip like the : Spartan-3E XC3S500E-FG320
  3. Run the synthesis process and examine the RTL view and the technology view. Annotate and commend the differences.
  4. Prepare a VHDL test bench file from the template and adding input stimulus.  VHDL test bench example Circuit_W_tb.vhd.
  5. Run the simulation process and extract the truth table from the inspection of the logic analyser display.

3.- Development

4. Test and verification

 

October 3  COMUNICAT:

Amb motiu dels episodis de violència, injustificada i injustificable exercida a Catalunya l’1 d’octubre per la guàrdia civil i la policia nacional, manifestem el nostre rebuig, la nostra indignació i la nostra condemna més enèrgica.

A la UPC creiem que l’ús de la força contra els ciutadans i ciutadanes és intolerable en democràcia i que la violència –per definició–, no pot ser mai proporcionada.

Més enllà de les diverses posicions polítiques de totes les persones que integren la comunitat de la UPC, coincidim a reiterar que l’única via possible en qualsevol conflicte és el diàleg i no ens cansarem de reivindicar-lo com a única arma legítima en democràcia.

Per tot això, la UPC se suma a l’aturada de país prevista per a demà, dia 3 d’octubre.

Se suspenen les activitats i els edificis romandran tancats

Atès que la UPC s’adhereix a l’aturada de país del 3 d’octubre, se suspenen les activitats, els edificis romandran tancats i no hi haurà serveis mínims.

 

October 2

let’s start the project P2, on simple combinational circuit design discussing how a VHDL file looks like: entity and architecture. Let’s describe the Circuit_W using its structural equation. So that by October 4, we can use this file (Circuit_W) adapted from here as the source file for running the VHDL synthesis and simulation process to obtain its truth table.

It is possible to describe entities using two approaches for the architecture:

1) structural (circuit/equation)

2) high level behavioural description (algorithm/truth table).

 

September 27 (today is Monday at the EETAC)

Today we’ve discussed about the many different projects that can be solve applying in some way or another the basic concepts such as maxterms, truth table, etc.

Solve any of these Circuit C, Circuit_K, Circuit A or Circuit B

1. Analysis for determining their truth table;

2. Design of different type of circuits from the initial truth table:

  • Project: Design a XOR of 3 inputs using only NAND of 2 inputs. Remember that the problem solution must be organised as follows:
    • Specifications and theory.
    • Planning.
    • Development of the plan.
    • Test/verify/check and discuss the solution.

 

September 26

Today we’ve solved a tutorial on the use of Minilog.exe application to minimise logic functions.

  • Project 1: From the truth table of the function W 0 f(D1, D0, A, B) obtain a circuit (Circuit 3) that is derived using minilog and SoP.
  • Project 2: Transform the previous Circuit_3 into a new one where all the gates are NOR.

September 20

Firstly, we’ve discussed about the 3rd and 4th methods for analysing a given circuit based on solving the circuit manually, this is using concepts like SoP or Pos, maxterms and minterms and the Boolean tricks for transforming logic terms.

–  Apply the same tutorials for solving Circuit_C and any other circuit you like.

Secondly, we’ve seen the design concept, where the initial data (specifications is the truth table), and so, you like to obtain (synthesise) different type of circuits: canonical, simplified, using only-NAND, using only-NOR, etc.

So, the next Monday class will be for minimising circuits using espresso algorithms (minilog or Logic Friday).

 

September 19

  • This is today’s Circuit_W that we have adapted in Proteus from this original one in the Proteus tutorial:

  • This is today’s equation.txt for run WorframAlpha calculations

September 18

This is the idea for organizing how to study and report each problem/project (now using sheets of paper, later using a word processor):

  1. Specifications
  2. Planning.
    1. Detailed plan 1
    2. Detailed plan 2
    3. …..
  3. Development
    1. Development of the Plan 1 to find the solution
    2. Development of the plan 2 …
    3. …..
  4. Test/verify/check the solutions

And this is the general plan for the P1, which has this simple specifications: Let’s obtain the truth table of the Circuit_C

  • The other day I forgot to tell you that I’ll only answer your emails if you follow these rules.

September 13

This is the course starting point: P1 on circuit using logic gates. We’ll try to solve a circuit every week and a synthesis or design project every four weeks when the chapter ends.

This is my timetable in case you like to ask questions or have some tutorial time.

Let’s analyse the Circuit_1C and the Circuit 1D in different ways in order to get in touch with the Boole’s Algebra. Analyse (and this is an example concept map) means to deduce its truth table, thus the way it works.

  • Check your Citrix credentials once the Receiver installed in your PC and through this web:

September 12

Question: What if I cannot attend class until next week?

Answer: Hi, I think that it is not a problem if you cannot attend classes until the next week. We’ll discuss the P1 which is online, so you can study it by yourself. 

Try to find two mates of the same class-subgroup for organising a cooperative group for solving lab projects and exercises.

Regards,

 

RPi – Capítol 3: Circuits electrònics

7 de juliol

Avui triarem projecte (especificacions, planificació, desenvolupament i test) per grups de treball i ja personalitzarem les discussions als requeriments de cada grup. El treball final es pot presentar per email fins al dia 14 de juliol. Podeu usar els materials fins aquest dia i discutir els vostres projectes amb l’instructor.

6 de juliol

El que em cal destacar és l’ús d’interrupcions per poder detectar canvis de nivell lògic en polsadors.

P12: Per poder dissenyar circuits digitals ja de certa entitat necessitem basar-nos en el concepte de FSM (màquina d’estats finits) o sistema seqüencial i de com s’estructura el programari en Python per resoldre les tasques que ha de dur a terme el diagram d’estat de la FSM. Hem discutit l’exemple del semàfor, que a partir d’una planificació inicial, es pot anar complicant seguint diverses fases.

P13: I a partir d’aquests projectes ja podrem introduir-nos en sensors i interfícies més complexes o d’alt nivell (SPI, I2C, etc.). Hem comentat el tema del bus I2C en què amb un parell de cables, serial data (SDA) i serial clock (SCL) es poden connectar multitud de sensors cadascun d’ells amb una adreça diferent. I la possibilitat d’adaptat els nivells de voltatge (de 5 V a 3,3 V) quan el sensor s’alimenta a aquesta tensió de 5 V no suportada per la Raspberry Pi.

5 de juliol

P9: Hem introduït el llenguatge Python perquè és el que més s’ha utilitzat en el món de la Raspberry Pi fins ara. I per tant hi ha molt de material, llibres i exemples per poder començar còmodament.

P10: Però si voleu per ara, o potser per més endavant, teniu disponibles biblioteques de funcions d’interfície per una quants llenguatges més.

P11: Aquí comencen pròpiament els exemples amb el connector GPIO. Hem fet un parell de circuits amb LED i amb polsadors.

  • Insistim en l’anàlisi dels circuits i dels programes de mostra amb l’objectiu de dibuixar el seu diagrama de flux.

RPi – Capítol 2: Aplicacions estàndard d’escriptori i programació

Dimecres 5 de juliol

P7:  Quines aplicacions educatives en general us interessen?

P8:  Si voleu convertir la Raspberry Pi en un servidor web i/o de WordPress.

Fixeu-vos que si ho voleu, ja podeu concentrar-vos o intensificar en el desplegament d’alguna aplicació contreta: simulació de circuits, eines ofimàtiques, construcció d’un mediacenter, etc.

 

Dimarts 4 de juliol

P5:  Què tenim a l’escriptori Raspbian?

P6Mediacenter KODI. Recomanable d’instal·lar també en un PC per provar-lo i habituar-se al seu entorn.

 

RPi – Capítol 1: El micro PC Raspberry Pi

Curs d’introducció a la Raspberry Pi.

4 de juliol de 2017

P3: Simplement presentar alguns comandaments senzills en mode text del sistema operatiu. També l’entorn gràfic, que s’assembla al Windows de Microsoft. Realment el Linux, amb les seves variants (Ubuntu, Debian, Linkat,(proposat pel Departament d’Ensenyament) etc., dona una alternativa molt vàlida en codi obert al Windows 10.

P4:Control i ús remot de la Raspberry Pi. Haurem de permetre que la R-Pi 3 tingui habilitades les interfícies VNC i SSH.

PuTTY: Connexió entre ordinadors SSH en mode text. La versió de la Raspberry ja està instal·lada per defecte.

VNC: La versió RealVNC ja està instal·lada gratuïtament a la Raspberry Pi. Modes viewer i server.

 

3 de juliol de 2017

Comencem pel primer treball P1 del curs. Instal·lació del kit i conceptes bàsics de la Raspberry Pi.

P1: Instal·lació bàsica. Configuració del teclat.

  • En primer lloc canviarem el password original “raspberry” de l’usuari pi.
  • Com es pot escollir el sistema operatiu? Perquè la targeta que subministra el kit per defecte ja arrenca per defecte en Raspbian. Entre quants sistemes operatius podem triar? Imatge NOOBS.
  • Com es descarrega la imatge des de la web oficial? Com es fa una còpia de seguretat de la memòria SD per si hi ha problemes, se’ns desconfigura i hem de tornar enrere?

P2: Data i hora. Ens hem trobat que els tutorials funcionaven en unes Raspberry Pi i no pas en altres. On està el problema?

Connexió manual (sense DHCP) a una una adreça fixa d’Ethernet, aprofitant que els llocs de treball del laboratori tenen cable i connexió a un switch. Així no cal entrar cada dia com usuari convidat.

  • Revisar els fitxers de sistema on es guarda la configuració de la WI-Fi i de cable Eth0.

 

CSD – P12: Real time using TMR2

Thursday 25

  • This is a new paper precisely on the key importance of the CLK device: Liming Xiu, “Clock Technology: The Next Frontier“, IEEE Circuits and Systems Magazine, 2017.  Perhaps you manage to download the full PDF from a UPC computer like Citrix using this eBIB tool. If not, ask me by email, and I’ll send it to you. It’s interesting to see how deep goes the research subject thinking only on CLK issues.
    Let’s introduce the way to program an application using the TMR0, so that later you can program a similar embedded timer peripheral in the PIC18F4520 microcontroller: the timer 2 (TMR2).

The idea of real time (seconds, minutes, etc.) is developed around counting pulses from a stable and accurate crystal oscillator.

This is the class discussion (1) and (2), where some ideas were given around the way to study the tutorials and how to program the TMR0 to develop applications like counting people coming into the library (events counting) or counting real time (timer from a precision CLK source).

Use the tutorial in P11 (fixed 18.5 s timer) to see how your sketches can be translated to C code.  It’s convenient to print in colour this code and analyse it. And the same with the timer structure, print the 3 pages of the PIC18F4520 datasheet chapter on TMR0.

 

CSD – P11: Adding an LCD display

May 23

In this P11, we’ll enhance the basic FSM, the Johnson counter developed in P10, with an LCD display to be able to write  ASCII messages, for instance indicating the the internal state of the machine, like: “Click the Start button”, or “State #1”, or “Click to Stop the sequencing”, etc.

Thus, you can attach an LCD to P10 when you have finished at least one of the P10 design phases.

Adding the LCD means learning about the peripheral itself, like the standard LM032L, and finding a library of C functions compatible with the C compiler (XC8) for the high-level handshake with the device . This is an introduction to the Microchip Peripheral Library (PLIBS). And, it may be even automatised using a tool like the MPLAB® Code Configurator (MCC).

CSD – P10: FSM using microcontrollers. A 6-bit Johnson counter

May 27

Let’s readjust the project phases and grading after some feedback from you. It looks like that solving the Phase #1 takes more time than initially estimated:

Phase #1 –> 8 p; phase #2 –> 2p;  phase #3 –> optional

Phase #3 can be incorporated later in P11 along with the LCD display.

May 24

This is a checklist for P10 proposal, as you has asked me in class.

Thursday 18

  • Today we’ve had an important tutorial class on the basics of FSM applied to programming microcontrollers studying the BCD_Counter. You can continue the tutorials by your own because the required materials are online. The idea is to adapt what you’ve learned on the design of the 6-bit Johnson counter.

Wednesday 17

  • Compiler data types and variables. Most of our variables in these introductory programmes will be “char”, which occupy a byte of RAM memory.

Tuesday 16

This is the project discussion (1), (2) on the Johnson counter to be implemented in this P10. How to solve a basic sequential circuit in C and using a microcontroller?

To comprehend the main ideas, and to plan your project, follow the tutorial examples BCD_counter, and the 74HCT4017 chip.

 

 

 

CSD – P9: Introducing microcontrollers. Basic I/O. 1-digit BCD adder

May 24

This is the checklist discussed containing most of the concepts.

May 20

Question:

I am doing P9, but I have some doubts about how to write the code. I download the PIC18F4520 from development of digsys web, but I don't know how to write the code. I am following the steps of init_system, read_inputs, truth_table and write_outputs, but I don't know exactly what I have to write. 

Answer:

Well, this is a general question ... better to find some time in office on Monday before 11h or after 16h, so that we can program something. 

Here you are some insight on how to start. The code I gave you that was run in class has only some connections and only the variable Value_Cin implemented in read_inputs(), so:

1. Start a project using both hardware and C source files. 
2. Compile and run to watch the variable Value_Cin.
3. Add some code to read_inputs(), for example to read the A(3..0) and convert it to Value_A. Firstly add the wires in the hardware circuit, and draw in paper the bitwise operations required. This is example of how you can organise the reading of a variable. 
4. Compile and run to watch the variable Value_A.
5. Etc... read B(3..0) the same way. 
6. Check if error in the A or B range.
7. Implement the truth table. If no error, (1) start adding in binary, and later (2) implement the BCD correction algorithm. 
8. Write the outputs. These (1) - (2)  are examples on how to write a given variable using bitwise C instructions. 
9. Run and check it all. 
10. Print your C code and a couple of images on how the circuit works. 

regards,

May 11

Comments on planning the P9. After having run the tutorial examples, the general idea is: 1) understand the problem, 2) plan a small step like reading an input variable, 3) develop the project so that you can 4) test it. Once it works fine, add some new instructions, for example for reading another variable, and repeat it all.

Meanwhile you solve these examples, it is recommended reading about microcontroller architecture and programming in any book or web page. Browse the vendor web sites too, like microchip.com.

Browse previous blog entries on P9 (1) to see similar class notes and ideas.

May 9

We’ve discussed the basics of microcontrollers (theory and tools), and we’ve explained how the tutorial example Dual_MUX4 is organised and how you can run the IDE to obtain the output COF file to enable debugging.

This is a tutorial, thus the C code is complete. However, in the BCD_Adder, better to go step by step, for instance reading only Cin pin and watching the variable Value_Cin to see if it’s been captured correctly compiling and debugging repeatedly.

May 4

This is the architecture of the PIC18F4520 to be used in this Chapter 3 on microcontrollers.