NOTE: Citrix virtual has not been working for two days now. It cracked or hanged on Saturday and it cannot be accessed. There is no maintenance service on weekends and it has to be repaired next Monday. So, we’ll delay de P_Ch2 due date by Thursday 14 at 13.00.
December 7 (more questions and answers by email)
We have a doubt and it is to check the number of registers of the clock generator.We only find this on the blog: “The name of the source file is JK_Flip_Flop.vhd. Run the EDA tool to synthesise the circuit and print and comment the RTL schematic. Check the number of registers (DFF) used in the target chip. In this simple example, the answer has to be a single DFF register.“
Yes, if you are synthesising a single JK-FF which is a 1-bit cell of memory, only a D-FF is required (it is a state machine of 2 states).
Now imagine that our CLK_generator has a single output like CLK_20Hz_SQ and the OSC_CLK_in is 50 MHz. So, it has to divide by 2.500.000 and so, the number of bits required to reach such a large counter of 2.5M states is: 22 (with 22 bit you can count in binary up to 4.194.304). In this case you need 22 D-FF. The summary report of the synthesis EDA tool has to show you this information on the number of registers D-FF used.
Yes but I can not find it here: Perhaps it is inside the synthesis report? I found it but I am not sure…
I see that “number of slice flip-flops” = 31. Or instead: 7-bit counters 3*7 = 21; 5-bit counters 1 *5 = 5; and 5 registers == 21+5+5 = 31. So, this is the number of D-FF that your design is using. You can check with your plan, whether this number is correct or not. As you see, every slice in the Spartan 3E contains a pair of memory cells data flip-flop. Time to time is convenient to read a bit of the databook, the technology of the programmable chip, because by now you will be able to identify a lot of logic and arithmetic blocks.
December 6 (questions and answers by email)
Hi Francesc, We have already finished the Timer_MMSS but we have a few questions:
1- Is it necessary to include the code to translate the BCD signals (DMT, DMU, DST, DSU) into 7-segment (BCD_7seg_decoder)?
No. This issue belong to the optional section 5: prototyping the design in a board like the NEXYS 2 from Digilent. You’ve invited to do it later, for instance by January after your exams. This is multiplexed display system (mds) in Proteus (video) from former 11/12Q2 term that was used there to implement a bicycle speedometer. This is the complete component MDS for adapting the NEXYS 2 which must be included in the top Timer_MMSS_NEXYS2 to drive the 7-segment displays with the MM and SS data.
2- Is it necessary to create the Button_synchroniser inside the Control Unit?
No. This issue is optional too. It allow me to explain you another concept: the synchronization of external signals to better work with a synchronous circuit and avoid uncertainty and improve reliability. But as said, it’s optional. It is the FSM that has the 3 states shown in the whiteboard.
3- We have created a test bench to test the Timer_MMSS but there is a problem, the simulation is so slow that it is impossible to see how the Timer works. We think that it is because of the CLK input is 50 MHz and the signal it has to count down is 1Hz (it takes a lot of time to generate the 1Hz signal). Something similar happened in the ClockGenerator test bench too.
Yes, it’s predictably too slow due the many frequency divisions from the initial CLK of 50 MHz. A way to speed up the circuit response while simulation is “fake” the frequency dividers, for instance the freq_div_125. Leave it as it is, but simply replacing the:
CONSTANT Max_Count : STD_LOGIC_VECTOR(6 DOWNTO 0) := “1111100”; — 124
CONSTANT Max_Count : STD_LOGIC_VECTOR(6 DOWNTO 0) := “0001001”; — 9 — > the same number of wires, but more faster (it is a divider by only 10 now), so it’ll speed up the simulation (the 1 s period is now 12.8 ms). Here you are a helpful test-bench with convenient times for clicking the buttons and a picture. (Later on, when doing it for real in a board if this is the case, replace the constant Max_Count to its original value 124, to obtain the “real-time” of 1 second).
Thank you very much for your interest and engagement in the subject and the quality of your questions that will help everybody else to succeed in solving this project.
December 2 (questions and answers by email)
- HINT: Here you are the top architecture of the dedicated processor Timer_MMSS adapted from this schematic discussed in class. The components’ architectures are empty now, but the EDA tool synthesise it to recognise an RTL view picture like the one below (click to expand):
- How to proceed with the design of the CLK_generator (all the section 1 in assessment list)?
1) Study the symbol and the plan. Comprehend why such frequency dividers and TFF are used and chained together.
2) Study the translation to VHDL of a counter/frequency divider block like Freq_div_100 available below by Nov 20 for the light_system_NESYS2 project (source files). Here you need to generate Freq_div_125, Freq_div_80, Freq_div_20, and a Freq_div_2 (hint: this is the component solved in 2 different versions: V1, V2, choose one of them). Adapt too the schematic CLK_generator.
3) Convert to VHDL your plan, synthesise it, inspect the RTL and test the CLK_generator behaviourally and at the gate-level in order to be able to measure the propagation time t_CO and the maximum frequency of operation f_max.
- How to proceed with the design of the Counter_MMSS and the datapath blocks (all the section 2 and the 3.1 in assessment list)?
Look at the symbol sketched in this picture, which is the first item in the specifications of the datapath. As we discussed in class, better you, as a cooperative group, do not go away from the design path that we’ve discussed together and is reported in the blog:
1) Study how the (BCD 2-digit synchronous) counter_mod24 works, based on counter_mod16 universal binary counter. Take your time because your objective is to design a very similar block: the counter_mod60
2) Once understood, modify the counter_mod24 to adapt it to be the counter_mod60. Synthesise and test it using the same testbench stimulus signals that I gave you for the counter_mod24.
3) Use 2 blocks counter_mod60 to build the Counter_MMSS which is precisely the Chip1 in the datapath. Synthesise and test it using the same stimulus signals as before.
4) Finish the datapath block adding to the schematic the MUX_2 Chip2 and Chip3 and Chip4 (Chi3 and Chip4 can be replaced by simple AND gates. Print its RTL view.
- How to proceed with the design of the Timer_MMSS (section 3 in assessment list)?
Only once the sections 1 and 2 are completed (the schematic of the CLK_generator and the datapath). Basically it is about writing the Control_unit FSM in a single file, and complete the top schematic composed of the Chip1 (datapath), Chip 2 (control_unit) and Chip 3 (CLK_generator)
1) Study the plan for the control_unit. State diagram, etc.
2) Adapt the file from Nov 20 on the light_system FSM.
3) Write the top schematic Timer_MMSS and synthesise it. Inspect the RTL and try to simulate it inventing a testbench for the push-buttons.
P_Ch2 due date: December 11. This is the organisation and assessment checklist. Thus, working in your cooperative group, you can go step by step solving one section at a time until you complete the different circuits involved in the project. Ask questions when necessary.
The internal architecture of the datapath and the FSM for the control unit:
And the FSM for the control unit. Additionally, you can even add another FSM component: the start button synchroniser, able to generate a single pulse when clicking:
We’ve discussed the P_Ch2 specifications (MMSS_timer) and how to start planning it.
- The programmable timer implemented as a dedicated processor composed of a datapath and a control unit.
- On how to divide frequency by a number N (freq_div_N) and how to square signals:
- And so, the idea for the conception of the CLK_Generator:
The same Thursday class at the same time, but with more materials to discuss:
- The P. 2.3.6 is the building block universal Counter_mod16 discussed in class. This is the plan (1) and (2) conceived as a single file FSM, and this is its VHDL description and example test bench in case you like to run the EDA tools for synthesising and testing. This below is a timing diagram:
- To learn better how to implement truncated counters, perhaps you like to try first the simpler project P. 2.3.7.
– This is a solution for the plan A: hierarchical design along with its translation to VHDL for you to develop the project and simulate it as shown below:
– This is a solution for the plan B: single file FSM design along with its translation to VHDL for you to develop the project and simulate it. You must obtain the same timing diagram above when zooming all. And below is the image of the CLK to output propagation time measurement obtained when running the gate-level simulation:
Try to finish the projects, ask questions and do not hesitate to use my office time. We’ll schedule another class for solving problems by mid December.
A 1-hout class (13:00-14:00) for solving example problems from the CSD collection or previous exams.
This is the discussion on the P. 2.3.5 of the collection: an hour up/down counter (synchronous BCD counter module 24 with the option of two output codes, 00 – 24, and PM/AM) :
- Understand the problem (specify it), and then infer a plan, like: a) convert a counter_mod16 into a counter_mod10, and b) use 2 counter_mod10 to implement the hour_counter. This is the full discussion (there was a bug corrected with the help of Guillem Delgado). This is the complete project development using the many components and below is a demonstration of waveforms:
Perhaps you can study the problem better if you consider for simplicity that firstly the hour_counter goes only UP.
The Counter_mod60 for the P_Ch2 can be solved in the same way.
- P7: Data and shift registers. Units 2.7 and 2.10 have examples of these basic sequential building blocks.
- This below is the P_Ch2 specification (MMSS_timer). Due date: December 11. It is a programmable timer like a commercial one: 2 buttons to setup the real time (MM:SS) at a 20Hz rate, another button to start (ST) the down-counting and another one to stop (SP) the alarm. There is a LED to indicate that the count down has reached 00:00 and also a sound wave of about 1.5 kHz period. The time-base is derived from a 50 MHz quartz crystal oscillator. The system can be implemented in the NEXYS 2 board.
P7: Let’s design counters, data and shift registers.
Below there are some notes of theory on counters. Play with the counters modelled in Proteus and finish the design of the Counter_mod16: 1) Specifications; 2) Planning; 3) Development; and 4A) Test functional, 4B) Gate-level. Determine the maximum speed of the counter targeted for an Spartan 3E XC3S500E-320
General ideas on the universal counter (symbol, function table, state diagrams. Write down an example of timing diagram and infer a plan using a FSM.
Using these strategies you can build many counters: binary, BCD, One-hot, Gray, Johnson, etc.
You can expand the number of states chaining counters together in a given way: BCD modulo 60 counter, binary 1024, etc.
Probably, the P_Ch2 will be de design of a real-time clock derived from the Digilent NEXYS 2 50 MHz oscillator. A programmable timer for instance.
Let’s finish the light_system FSM project:
3. Development. Let’s continue the light_system problem. Find a similar VHDL file and adapt it to the FSM.
4.- Test and demonstration. Run a functional and a gate-level simulation to check that the circuit works as expected.
These are the example files once adapted and this below is a typical capture that shows how does it work:
- Additional demonstration: This is the complete project light_system_top prototyped in a NEXYS 2 board populated with a Spartan 3E FPGA (follow too the tutorial on the LED flashing light, which is very similar). This is the class discussion on the 3rd and 4th design steps:
- Class at the 128B for the group 3GT3 (or any other student who may like to solve problems). A repetition of the Thursday class.
The class discussion:
- Class at 239V for the group 3GM1 (or any other student who may like to solve problems). We’ve solve the problem 2.2.3 of the CSD collection. Material that is also prepared as a tutorial in P5 learning materials: Asynchronous circuits.
- Go and vote for the rector of the UPC
- Infer the D-FF from an RS-FF.
- P6: Using the D-FF as the memory cell in the state register of a FSM. Example of a FSM: Classroom ON/FF lighting system.
This is a list of the projects solved in P6.
This is a list of the projects solved in P5.
Let’s continue with the internal design of the 1-bit memory cells:
P5. Let’s start the Chapter 2 with the 1-bit memory cell: RS latch (asynchronous), and JK, D, T, and RS flip-flops (synchronous). This is the new building block that is going to be used along with combinational circuits to implement finite state machines (FSM).
How to deduce an RS flip-flop from a RS latch? Use these notes as the starting ideas on sequential systems