Important note: Let’s give the last project P_Ch3 some more days. The new due date will be on Saturday 20 at 15.00.
This is an update of the P-Ch3 checklist discussed by December 20.
This zipped file contains a demonstration of the complete project (up to phase #4).
In my opinion this is a meaningful and complete way to finish this CSD introductory course on digital electronics. A real circuit (a subsystem) that you can find everywhere in hundreds of applications like a timer, solved using two different technologies:
– Hardware (P_Ch2): Programmable devices like CPLD and FPGA describing the circuits in VHDL
– Software (P_Ch3): Microcontrollers programmed in C
You may consider these examples here in CSD as an starting point for further developments and projects in this area.
Question: … on the way the dec_1:2 and the counter_mod2 can be translated to C.
Answer: First of all, realise the function of such decoder dec_1:2. It is simply to generate this two codes for driving the transistors’ bases:
01 –> To light the tens (because the 7-segment digit is active low) and blank the units.
10 –> To light the units and blank the tens
And so, this sequence: 10, 01, 10, 01, 10, … has to go indefinitely to refresh both digits at 20 Hz. So, to generate two codes you need simply a counter_mod2 of a single bit as output. However, to generate a counter_mod2, you needn’t a counter, but toggle a variable like:
Value_Q = ~Value_Q; (bitwise NOT)
In this way the variable is 0x00 or 0xFF, and it works because (if) when Value_Q == 0 –> Value_CA = 1; (0x01), else Value_CA = 2 (0x02);
You need only some lines of code placed in the write_outputs() for the mechanism of multiplexing digits.
Try it placing a breakpoint and observing that every 50 ms Value_CA is 1 or 2. (0b00000010, 0b00000001, …)
In this way, you can write this variable in the corresponding pins at the same time as the corresponding Value_Tens_7seg or Value_Units_7seg. In my hardware, I see that they are PD4 and PD5, so: PORTD = Value_CA<<4;
Notice that for four 7-segment digits, yes, you need a counter_mod4 to generate Value_Q = 1110, 1101, 1011, 0111, … decoding (dec_2:4) only one ‘0’ at a time to drive a single transistor’s base at a time.
Question: We have a lot of doubts about the software of Counter_mod60. Our main question is: Do we have to define 60 states in the code like I show you in the attached picture? Doing that, for the Timer_MMSS we’ll have to write 3600 states! Another way that we think is to define 6 and 10 states for separated and then go them alternating with the CA_L. Maybe we are wrong, and the are another correct procedure. We don’t know how to advance…
Answer: No, it is a lot better to chain 2 counters (a Counter_mod10 and a Counter_mod6) as indicated in the schematic, generating the convenient variables, like Value_CET. Please, think first and have a plan, never try to write 3600 states, this is not the way.
Chaining 2 counters (or many more to get later a Counter_MMSS or a Counter_YYMMDDHHMMSS) is the right way.
I’ve given you in the PDF the general ideas and the flowcharts that can be easily translated to C, and here in the blog (January 3) the sequence of steps to proceed. If you like to comment specific instructions in C, better find me in office next Monday.
Do not mix blocks, because for instance, the CA_L(1..0) has to be generated in the write_outputs function when solving the multiplexed display system, not now that you are solving the main counter block the outputs of which are simply the variables Value_DTens and Value_DUnits that you can watch whether they go from 00 to 59 or not.
Question: I am writing to you to ask about the ISR. Attending to the flow chart given in digsys, the Value_Freq_div20 only advance once Value_Freq_div3 reach value 3 (Value_Freq_div3_max_count). Every time that Value_Freq_div3 reach it’s max count, the CLK_MUX_Flag will be 1. I have been programming it, but I can’t get the two Flag = 1, only I have the CLK_MUX_Flag = 1. How can I get (or store) the two Flags = 1?
Answer: As the block diagram indicates, they are two counters chained together.
You set the CLK_MUX_Flag = 1 because the first counter has reached its terminal count.
So, at the same time that you do CLK_MUX_Flag = 1; you also have to do Value_Freq_div3 = 0 to initialise it again, and Value_Freq_div20++, which increments the count of the next counter mod 20.
And when this second counter reaches its last state, then: CLK_Flag = 1 and Value_Freq_div20 = 0. That all, an exact translation of the flow chart for the ISR:
In this way, if the input frequency for the external interrupt is 60 Hz, there will be a CLK_MUX_Flag every 50 ms (20 Hz) and a CLK_Flag every 1 s.
Use a breakpoint in the ISR and ‘run’ several times to see this timing.
This zipped file contains a demonstration on how the Counter_MMSS works (P_Ch3 Phase #3).
As you have noticed, the datapath resources, the counters, are controlled and work exactly in the same way. The only difference relies in the counter capacity. The counter_MMSS has more states (3600) than the counter_mod60.
In this way, to make the design easier, if you like, you can develop the Phase #4 of the P_Ch3 (the control unit that handles the complete Timer_MMSS) using whatever counter: a) the Counter_mod60 from phase #2, or b) the counter_MMSS from phase #3.
Do not try to solve this phase #2 on the Counter_mod_60 in a single step. Instead, after having studied the given planning, follow for instance like this, thus you’re able to get partial results:
- Generate the flags coding the interrupt service routine. In step mode and using breakpoints, you’ll see that for an external signal of 60 Hz, the CLK_MUX_Flag is 50 ms and the CLK_Flag is 1 s.
- Generate the Counter_mod60 and watch the variables Value_DTens and Value_DUnits. Then, translate them to Value_Tens_7seg and Value_Units_7seg
- Generate the multiplexed system (in write_outputs) to drive both 7-segment display alternatively at 20 Hz rate.
- Add the SelCLK to be able to modify the counter speed (1 Hz or 20 Hz).
[This is how it looks like, as being in the L129 session and me showing you how it works. Run the Proteus simulation: the hardware along with the ‘*.hex’ that you can place at the same folder once unzipped. The digit flickering observed is due to the simulator and it is not seen in the real prototype].
Email questions: First of all, how can we translate the frequency divider that we have to use (for the 20 Hz and the 1 Hz CLK) into the hardware and software?
Secondly, how does the CA_L output in the counter modulo 60 work?
Answers: I gave you yesterday some ideas here in this paper posted in the blog.
As you see there, the frequency divider is generated at the interrupt service routine as flag variables (CLK_MUX_Flag, CLK_Flag). Basically, you observe a counter modulo 3 chained to a counter modulo 20, from an starting frequency of 60Hz. And so, the flags are used when necessary in the main program: the CLK_Flag for running the main Counter_mod60 at 1 Hz rate, and the CLK_MUX_Flag for toggling the digits in the write_outputs() at 20 Hz rate.
Well, each common anode signals drives a transistor PNP. A ‘0’ (low) saturates the transistor converting it into a switch ON, so that the current for the 7-segment display flows to the segments a_L, b_L, …, g_L which are driven by a ‘0’. You realise that at any given time, only one common anode signal is at ‘0’. When the digit Tens is activated, the code that has to be represented as Tens is also selected to drive the cathodes. You can see how the hardware circuit works here (December 6)in this Proteus example for 4 7-segment digits.
This PDF is another bit of help for you. So that you can focus your attention and fix some ideas on how to plan the phase #2 on the design of the Counter_mod_60 taking advantage of the previous analysis of the Counter_mod10.
As you knowe, you can program in C in any way, but here for these low-level hardware-dependent projects, it is a lot easier if you take advantage of all you know from Ch2, speciality if you have to work in group with your team mates and receive fast feedback from your instructors.
Ok, you been asking some questions by email on how to start the project P_Ch3 sequenced in several design phases here. This is the first phase completed in hardware (1) and software (2). So, you only have to develop and test and get results. Because this first phase is finished you only have to report the plan, which is the analysis of the hardware and C code given.
Questions and answers (Merry Christmas ad Happy New Year)
Question: I am writing to ask if you could send me some exercises of exams or something with solutions in order to repeat them and correct my errors.
Answer: Everything I’ve got is somewhere in the web. For instance:
– List of problems (at the bottom of pages from P5 to P10) that we’ve been solving this semester:
“A summary of projects proposed in the Px”.
– A collection of problems:
– Many exam problems form other semesters. Click any term here:
then click the test tab in each semester, for example:
Sometimes, the problems has a discussion attached. And sometimes better to discuss them in office time.
This is the last class and it we’ll be devoted to the organisation of the project P_Ch3 on the Timer_MMSS based on a microcontroller ATmega 8535. Dead-line January 17 23.00. The idea on designing the same application but with a different technology is to give you the opportunity to compare alternative designs for the same product, which is very important for an engineer: processing speed, PCB volume and number of components, power consumption, design time, flexibility to enhance the product to add new features, etc. Besides, it will be easy for you, considering the time available, if you know very well the specification and general planning of the application from P_Ch2.
Let’s divide the P_Ch3 project in 4 phases (see the list of projects), because it is not recommended to solve it in a single step (it is indeed a dedicated processor, with a control unit, a datapath and a CLK_generator). Therefore, a way to proceed is the following one:
- Phase #1. General organization. Study and adapt the P_Ch2. Suppose a 20 Hz oscillator attached to an external interrupt. Develop a Counter_mod10 with CE and UD_L control. Study and design a 7-segment decoder so that you can see the numbers in a digit. (2p)
- Phase #2. Design a Counter_mod_60 with count enable and reversibility features and attach the output to a multiplexed 7-segment display of D_Tens(3..0) and D_Units(3..0). Implement a frequency divider and a switch to select the CLK source to be a 20 Hz or a 1Hz external signal. (3p)
- Phase #3 Design a Counter_MMSS with count enable and reversibility features and attach the output to a multiplexed 7-segment display of DMT(3..0), DMU(3..0), DST(3..0) and DSU(3..0). (1p)
- Phase #4 Select one of the two options:
1) Finish the Timer_MMSS designing the control unit to manage the data-path. Study one of these options: how the Atmel training board 7-segment display works or how the LCD can be interface to this board to represent the 4 digits. (4p). [This phase can be build using the counter_mod60 from phase #2 in case you like to skip the phase #3].
2) Record a cooperative group 10 minutes oral presentation of the first 3 design phases of this P_Ch3 or the design of any other project of the course. (4p)
Microcontroller peripherals (you may like to study them when you have time after the exams or at summertime). Designing with microcontrollers adds some features like to any previous application, like:
(1) LCD display peripheral to represent MMSS and other information. See the P11.
(2) Peripheral Timer0 to generate an internal CLK_generator to replace the external CLK signal saving components. See P12. Programming correctly the Timer0 (or Timer1 or Timer2) , it is possible to generate the three signals of interest: CLK_1Hz_SQ, CLK_20Hz_SQ and CLK_1_6kHz_SQ. (The CLK_100kHz_SQ is not necessary here because the system will run the software infinite loop at a given speed that will depend on the number of instructions and the crystal oscillator frequency).
Repeat any project targeting another hardware platform, like Arduino or Raspberry Pi.
And today, we’ve been practising on the planning and development of the Counter_Johnson_6bit. See the whiteboards. We’ve solved up the section 3. The idea is that form now, you can add more sections or phases of code until you complete all the specifications.
Today, we’ve continued the analysis of the BCD counter, tutorial. In this way, we’re ready for solving the Counter_Johnson_6bit tomorrow in the lab.
– The use of breakpoints to watch how the program stop at a given C instruction and to follow the values of the variables.
– How long does it take to execute the infinite loop? How fast is for instance the CE pin sampled/polled/read)?
– How many OSC cycles are required to execute an assembler instruction? How can you find this information in the data-sheet?
– Which specific pins can be used to connect the CLK input?
– Which mechanism allows the detection of signal transitions (edge-sensitive)? Which mechanism is used to sample/read the digital value of a signal (level-sensitive)?
– How to detect that the system has been interrupted by an external signal like a CLK’s falling edge?
In P10 –> learning materials there are some other tutorials that can be run and analysed. Try them with the idea in mind in comprehending how the FSM concept can be implemented using a microcontroller.
P10. Let’s try to implement FSM using a a microcontroller, thus opening the possibility to design complex circuits based on components like counters and registers. Why not to think in the end about repeating the P_Ch2 (a real-time timer counting minutes and seconds, conceived as a dedicated processor with datapath and control unit) using now a single Atmel microcontroller programmed in C?
* This is the tutorial (BCD counter) (the example 2 here for Atmel) from which you can learn the basics of using interrupts and the design of a FSM
- The BCD_Adder module. This is the beginning of the design process that we’ve started in the lab all together. Please, finish it yourself (step by step, the read_inputs(), write_outputs() and the truth_table()) and ask me questions if necessary.
- Today, some ideas on the general planning of the BCD_Adder and how to write a variable to a given port pin. Tomorrow will be your turn to practice.
- New project using Atmel Studio 6.2. Let us see how to start a new project, compile and debug code using simultaneously both the Atmel Studio and the Proteus: learning step-mode of operation, code breakpoints, execution time measurement, and debug using the watch window. For instance, capture/sample/read the Ch2(1..0) input bits –> pict_1 (hardware connexions); pict_2 (Port C bit 4 as input, Port B bit 7 as input); pict_3 (code) ; pict_4 (results using the watch window).
- Let’s adapt now the tutorial to the BCD_Adder. Firstly the hardware, and then the software
P9: This below is the whiteboard discussion of the tutorial Dual_Mux4 hardware and software organisation. Tomorrow we’ll learn about how to read and write data from and to microcontroller port pins.
P9: Let’s start with microcontroller chips. The idea is to implement applications like the ones seen in previous charters but using a microcontroller and the C language. This course we’ll use an Atmel ATmega8535 chip from Microchip, Atmel Studio 6.2 integrated development environment (IDE) and Proteus VSM as the simulation tool.There is a tutorial example that we’ll discuss in class: Dual_Mux4.