Three concepts left in Chapter 1 that will be covered in this class:
1) Implementing logic functions using the method of decoders.
2) Implementing logic functions using the method of multiplexers.
3) Gate-level simulation to determine how fast is the synthesised circuit (propagation time/ maximum speed of processing).
In this picture you can see that the Adder_5bit propagation delay in a given transition is 9.1 ns, thus the maximum speed of procession is 109.9 MHz
Today’s class on integer arithmetic is very important. The two’s complement convention. We have discussed in detail the specifications and the plan to solve the proposed P4 as the P_Ch1. Stuff covered:
- Binary numbers, symbols, range, addition.
- Conversion from binary to decimal, decimal to binary, hexadecimal numbers.
- How to use the simple calculator in programming mode to works with bin/hex/oct/dec numbers.
- The general architecture of an arithmetic and logic unit (ALU) and an example chip: 74LS181. The idea of performing in parallel all the operations and then selecting only one result.
- How to represent positive/negative numbers (integers): two’s complement (2C) convention and range of values for a given number of N bits.
- Operations with integers, overflow flag (OV): which is the algorithm to detect an overflow situation?
- Play with the 8-bit adder/subtractor available in Proteus.
- Play with a similar arithmetic circuit: the 7-bit signed multiplier.
- Subtraction as a specific block build using individual Subtractor_1bit (see problem 1.4.3 in the CSD collection)
- Addition: R = A + B. Subtraction: R = A – B = A + (-B) = A + 2C(B)
- The idea of a XOR gate of 2 inputs as a programmable (CNTL) inverter/buffer to be used as a 2C generator module.
- The improved plan for a 10-bit 2C adder/subtractor. Use it in your P4.
NOTE. There is no more classes on P4/P_Ch1. It is a self-directed learning material for you to be solved in cooperative groups. When finished, follow the instructions to upload it at the Atenea platform task (one project per group) before the due date (October 31). Ask questions if necessary.
Today we’ve solved and tested an Adder_5bit (P3_4) for practising on hierarchical designs using components and signals.
P3: Let’s explain the main ideas on VHDL hierarchical design based on COMPONENTS and SIGNALS at the same time that we learn arithmetic circuits. Basically, study, run and test Adder_1bit (P3_1), Adder_4bit (P3_2) and MUX_8 (Plan C2) (P3_3) tutorials.
On the other hand, learn how to add binary numbers using gates (Adder_1bit, Adder_4bit). Note how the 4-bit adder has two different plans: 1) ripple carry, 2) carry look ahead.
- This is the template for the P_Ch1. Upload it at the Atenea task before the due date.
The list of projects being studied in this P2.
1h – Presentation of different (specifications: idea, symbol, truth table, timing diagram, commercial chips, etc.) combinational logic blocks: decoders, encoders, multiplexers, demultiplexers, hex-7seg decoders, etc. The main idea here is that any block can be designed using different plans like it is shown in the MUX_8 example.
1h: Plan B of the MUX_8 design (P2_5). How to translate to VHDL the truth table or the algorithm of a circuit? Using schematics and flow charts.
Let’s design the MUX_8 chip. For example the MUX_8 using a structural approach (P2_4). These below are some of the ideas discussed in class:
The HEX_7SEG_Decoder tutorial on running the ISE (synthesis) and ISim (simulation) tools:
Project P2_2: Design the HEX_7_SEG circuit using a structural approach (equations).
Project P2_3: Design the HEX_7_SEG circuit using a behavioural approach (truth table).
NOTE: Complete the projects that we start in class. You must do it in order to learn correctly the specific content of the course. By now we have discussed up to 8 projects and tutorials for P1. (which is at least 8 x 4 = 32 individual dual face sheets of paper)
Be neat, fair and stick to the rules: every project in different sheets and organised as you know: 1) specifications, 2) planning; 3) development; 4) test and verification. And remember that each one of these four project sections goes in a different sheet of paper. Ask questions if necessary.
Today we’ve completed the example tutorial on running the VHDL tools :
- Specifications: Find the truth table of the Circuit_W using VHDL synthesis and simulation tools (This is the project in P2_1).
- The plan is:
- Write the VHDL source file from a similar file in digsys.upc.es (P2). VHDL source file example Circuit_W .vhd.
- Start a new project for a XILINX target FPGA chip like the : Spartan-3E XC3S500E-FG320
- Run the synthesis process and examine the RTL view and the technology view. Annotate and commend the differences.
- Prepare a VHDL test bench file from the template and adding input stimulus. VHDL test bench example Circuit_W_tb.vhd.
- Run the simulation process and extract the truth table from the inspection of the logic analyser display.
4. Test and verification
October 3 COMUNICAT:
Amb motiu dels episodis de violència, injustificada i injustificable exercida a Catalunya l’1 d’octubre per la guàrdia civil i la policia nacional, manifestem el nostre rebuig, la nostra indignació i la nostra condemna més enèrgica.
A la UPC creiem que l’ús de la força contra els ciutadans i ciutadanes és intolerable en democràcia i que la violència –per definició–, no pot ser mai proporcionada.
Més enllà de les diverses posicions polítiques de totes les persones que integren la comunitat de la UPC, coincidim a reiterar que l’única via possible en qualsevol conflicte és el diàleg i no ens cansarem de reivindicar-lo com a única arma legítima en democràcia.
Per tot això, la UPC se suma a l’aturada de país prevista per a demà, dia 3 d’octubre.
Atès que la UPC s’adhereix a l’aturada de país del 3 d’octubre, se suspenen les activitats, els edificis romandran tancats i no hi haurà serveis mínims.
let’s start the project P2, on simple combinational circuit design discussing how a VHDL file looks like: entity and architecture. Let’s describe the Circuit_W using its structural equation. So that by October 4, we can use this file (Circuit_W) adapted from here as the source file for running the VHDL synthesis and simulation process to obtain its truth table.
It is possible to describe entities using two approaches for the architecture:
1) structural (circuit/equation)
2) high level behavioural description (algorithm/truth table).
September 27 (today is Monday at the EETAC)
Today we’ve discussed about the many different projects that can be solve applying in some way or another the basic concepts such as maxterms, truth table, etc.
Solve any of these Circuit C, Circuit_K, Circuit A or Circuit B
1. Analysis for determining their truth table;
2. Design of different type of circuits from the initial truth table:
- Project: Design a XOR of 3 inputs using only NAND of 2 inputs. Remember that the problem solution must be organised as follows:
- Specifications and theory.
- Development of the plan.
- Test/verify/check and discuss the solution.
Today we’ve solved a tutorial on the use of Minilog.exe application to minimise logic functions.
- Project 1: From the truth table of the function W 0 f(D1, D0, A, B) obtain a circuit (Circuit 3) that is derived using minilog and SoP.
- Project 2: Transform the previous Circuit_3 into a new one where all the gates are NOR.
Firstly, we’ve discussed about the 3rd and 4th methods for analysing a given circuit based on solving the circuit manually, this is using concepts like SoP or Pos, maxterms and minterms and the Boolean tricks for transforming logic terms.
– Apply the same tutorials for solving Circuit_C and any other circuit you like.
Secondly, we’ve seen the design concept, where the initial data (specifications is the truth table), and so, you like to obtain (synthesise) different type of circuits: canonical, simplified, using only-NAND, using only-NOR, etc.
So, the next Monday class will be for minimising circuits using espresso algorithms (minilog or Logic Friday).
- This is today’s Circuit_W that we have adapted in Proteus from this original one in the Proteus tutorial:
- This is today’s equation.txt for run WorframAlpha calculations
This is the idea for organizing how to study and report each problem/project (now using sheets of paper, later using a word processor):
- Detailed plan 1
- Detailed plan 2
- Development of the Plan 1 to find the solution
- Development of the plan 2 …
- Test/verify/check the solutions
And this is the general plan for the P1, which has this simple specifications: Let’s obtain the truth table of the Circuit_C
- The other day I forgot to tell you that I’ll only answer your emails if you follow these rules.
This is the course starting point: P1 on circuit using logic gates. We’ll try to solve a circuit every week and a synthesis or design project every four weeks when the chapter ends.
This is my timetable in case you like to ask questions or have some tutorial time.
Let’s analyse the Circuit_1C and the Circuit 1D in different ways in order to get in touch with the Boole’s Algebra. Analyse (and this is an example concept map) means to deduce its truth table, thus the way it works.
- Check your Citrix credentials once the Receiver installed in your PC and through this web:
Question: What if I cannot attend class until next week?
Answer: Hi, I think that it is not a problem if you cannot attend classes until the next week. We’ll discuss the P1 which is online, so you can study it by yourself.
Try to find two mates of the same class-subgroup for organising a cooperative group for solving lab projects and exercises.